By Himanshu Bhatnagar
The emphasis of this ebook is on real-time software of Synopsys instruments, used to strive against a variety of difficulties noticeable at VDSM geometries. Readers might be uncovered to a good layout method for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, actual synthesis, and static timing research. At every one step, difficulties similar to every section of the layout circulation are pointed out, with strategies and work-around defined intimately. additionally, the most important matters comparable to structure, together with clock tree synthesis and back-end integration (links to format) also are mentioned at size. additionally, the booklet comprises in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding kinds, particular in the direction of optimum synthesis answer.
aim audiences for this booklet are working towards ASIC layout engineers and masters point scholars project complex VLSI classes on ASIC chip layout and DFT techniques.
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Extra resources for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® by Himanshu Bhatnagar